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CS61577 T1/E1 Line Interface
*
Provides Analog Transmission Line Interface for T1 and E1 Applications
* Drop-in Replacement for CS61574 with
the Following Enhancements: - Lower Power Consumption
-
Transmitter Short-Circuit Current Limiting Greater Transmitter Immunity to Line Reflections Software Selection Between 75 and 120 E1 Output Options Internally Controlled E1 Pulse Width B8ZS/HDB3/AMI Encoder/Decoder
( ) = Pin Function in [ ] = Pin Function in 2 R E M O T E L O O P B A C K 26
-
The CS61577 is a drop-in replacement for the CS61574, and combines the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating from a +5V supply. The CS61577 supports processor-based or standalone operation and interfaces with industry standard T1 and E1 framers. The receiver uses a digital Delay-Locked-Loop which is continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance. The receiver includes a jitter attenuator optimized for minimum delay in switching and transmission applications. The transmitter provides internal pulse shaping to insure compliance with T1 and E1 pulse template specifications.
-
* *
Interfacing Network Equipment such as DACS and Channel Banks to a DSX-1 Cross Connect Building Channel Service Units 28-pin PLCC, Lead Free 28-pin PLCC
TGND TV+
-
CS61577-IL1Z CS61577-IL1Z
MODE 5
(CLKE) (INT) (SDI) (SDO) TAOS LEN0 LEN1 LEN2 28 23 24 25
TCLK TPOS [TDATA] TNEG [TCODE] RCLK RPOS [RDATA] RNEG [BPV] 3
4
L O C A L L O O P B A C K 1
15 14 LINE DRIVER 13 16
CONTROL
PULSE SHAPER LINE RECEIVER
TTIP TRING
8 7
AMI, B8ZS, HDB3, CODER
19 20 17
JITTER ATTENUATOR
CLOCK & DATA RECOVERY SIGNAL QUALITY MONITOR
RTIP
RRING MTIP [RCODE] MRING [PCS] DPM [AIS]
6
DRIVER MONITOR 22 RGND
18
11 9 10 27 LLOOP (SCLK) 12 LOS 21 RV+
RLOOP XTALIN XTALOUT ACLKI (CS)
Preliminary Product Information
http://www.cirrus.com P. O. Box 17847, Austin, Texas, 78760 (512) 445-7222 FAX:(512) 445-7581
This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 200 Copyright (c) Crystal (All Rights Reserved) Semiconductor Corporation 1996 (All Rights Reserved)
MAY '96 -8/ `0 DS155PP2 DS155F
CS61577
RV+ 6.0 V TV+ (RV+) + 0.3 V Input Voltage, Any Pin (Note 1) Vin RGND-0.3 (RV+) + 0.3 V Input Current, Any Pin (Note 2) Iin -10 10 mA Ambient Operating Temperature TA -40 85 C Storage Temperature Tstg -65 150 C WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA.
DC Supply
(referenced to RGND=TGND=0V)
DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V Ambient Operating Temperature TA -40 25 85 C 400 500 mW Power Consumption (Notes 4,5) PC Power Consumption (Notes 4,6) PC 230 mW Notes: 3. TV+ must not exceed RV+ by more than 0.3V. 4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 5. Assumes 100% ones density and maximum line length at 5.25V. 6. Assumes 50% ones density and 300ft. line length at 5.0V. (TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V)
2.0 High-Level Input Voltage (Notes 7, 8) VIH PINS 1-4, 17, 18, 23-28 Low-Level Input Voltage (Notes 7, 8) VIL 0.8 PINS 1-4, 17, 18, 23-28 High-Level Output Voltage (Notes 7, 8, 9) VOH 4.0 IOUT = -40 A PINS 6-8, 11, 12, 25 0.4 Low-Level Output Voltage (Notes 7, 8, 9) VOL IOUT = 1.6 mA PINS 6-8, 11, 12, 23, 25 Input Leakage Current (Except Pin 5) 10 Low-Level Input Voltage, PIN 5 VIL 0.2 High-Level Input Voltage, PIN 5 VIH (RV+) - 0.2 Mid-Level Input Voltage, PIN 5 (Note 10) VIM 2.3 2.7 Notes: 7. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output. 8. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40A). 9. Output drivers will drive CMOS logic levels into a CMOS load. 10. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating.
2
V V V V A V V V
DS155F
CS61577
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V)
AMI Output Pulse Amplitudes (Note 11) 2.14 2.37 2.6 V E1, 75 (Note 12) 2.7 3.0 3.3 V E1, 120 (Note 13) 2.7 3.0 3.3 V T1, (FCC Part 68) (Note 14) 2.4 3.0 3.6 V T1, DSX-1 (Note 15) Load Presented To Transmitter Output (Note 11) 25 Jitter Added During Remote Loopback (Note 16) 10Hz - 8kHz 0.005 UI 8kHz - 40kHz 0.008 UI 0.010 UI 10Hz - 40kHz Broad Band 0.015 UI Power in 2kHz band about 772kHz (Notes 11, 17) 12.6 15 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 11, 17) -29 -38 dB (referenced to power in 2kHz band at 772kHz) Positive to Negative Pulse Imbalance (Notes 11, 17) 0.2 0.5 dB Transmitter Output Impedance (Notes 17, 18) 10 Transmitter Short Circuit Current (Notes 11, 19) 50 mA RMS Notes: 11. Using a 0.47 F capacitor in series with the primary of a transformer recommended in the Applications Section. 12. Pulse amplitude measured at the output of the transformer across a 75 load for line length settings LEN2/1/0 = 0/0/1 and 0/0/0. For LEN2/1/0 = 0/0/0 only, a 4.4 resistor is required in series with the transformer primary. 13. Pulse amplitude measured at the output of the transformer across a 120 load for line length setting LEN2/1/0 = 0/0/0. 14. Pulse amplitude measured at the output of the transformer across a 100 load for line length setting LEN2/1/0 = 0/1/0. 15. Pulse amplitude measured at the DSX-1 Cross-Connect for all line length settings from LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1. 16. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 17. Not production tested. Parameters guaranteed by design and characterization. 18. Measured between the TTIP and TRING pins at 772 kHz during marks and spaces. 19. Measured broadband through a 0.5 resistor across the secondary of the transmitter transformer during the transmission of an all ones data pattern with LEN2/1/0 = 0/0/0 or 0/0/1.
DS155F
3
CS61577
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V)
RTIP/RRING Input Impedance Sensitivity Below DSX (0dB = 2.4V) Loss of Signal Threshold Data Decision Threshold T1, DSX-1 (Note T1, DSX-1 (Note T1, (FCC Part 68) and E1 (Note Allowable Consecutive Zeros before LOS Receiver Input Jitter Tolerance (Note 10kHz - 100kHz 2kHz 10Hz and below
-13.6 500 20) 21) 22) 23) 0.4 6.0 300 60 53 45 160
50k 0.30 65 65 50 175 -
70 77 55 190 -
dB mV V % of peak % of peak % of peak bits UI UI UI
Jitter Attenuation Curve Corner Frequency (Notes 17, 24) 6 Hz Attenuation at 10kHz Jitter Frequency (Notes 17, 24) 50 dB Attenuator Input Jitter Tolerance (Before Onset 12 23 UI of FIFO Overflow or Underflow Protection) (Notes 17, 24) Notes: 20. For input amplitude of 1.2 Vpk to 4.14 Vpk. 21. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+. 22. For input amplitude of 1.05 Vpk to 3.3 Vpk. 23. Jitter tolerance increases at lower frequencies. See Figure 11. 24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase significantly when more than 12 UI's are input to the attenuator. See discussion in the text section.
4
DS155F
CS61577
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
6.176000 Crystal Frequency (Note 25) fc TCLK Frequency ftclk 1.544 ACLKI Frequency (Note 26) faclki 1.544 RCLK Duty Cycle (Note 27) tpwh1/tpw1 45 50 Rise Time, All Digital Outputs (Note 28) tr Fall Time, All Digital Outputs (Note 28) tf TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 25 RPOS/RNEG Valid Before RCLK Falling (Note 29) tsu1 150 274 RDATA Valid Before RCLK Falling (Note 30) tsu1 150 274 RPOS/RNEG Valid Before RCLK Rising (Note 31) tsu1 150 274 RPOS/RNEG Valid After RCLK Falling (Note 29) th1 150 274 RDATA Valid After RCLK Falling (Note 30) th1 150 274 RPOS/RNEG Valid After RCLK Rising (Note 31) th1 150 274 Notes: 25. Crystal must meet specifications described in Appendix A. 26. ACLKI provided by an external source or TCLK. 27. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached. 28. At max load of 1.6 mA and 50 pF. 29. Host Mode (CLKE = 1). 30. Extended Hardware Mode. 31. Hardware Mode, or Host Mode (CLKE = 0) 32. The transmitted pulse width does not depend on the TCLK duty cycle.
55 85 85 -
MHz MHz MHz % ns ns ns ns ns ns ns ns ns ns
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Crystal Frequency (Note 25) TCLK Frequency TCLK Duty Cycle for LEN2/1/0 = 0/0/0 (Note 32) ACLKI Frequency (Note 26) RCLK Duty Cycle (Note 27) Rise Time, All Digital Outputs (Note 28) Fall Time, All Digital Outputs (Note 28) TPOS/TNEG (TDATA) to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG (TDATA) Hold Time RPOS/RNEG Valid Before RCLK Falling (Note 29) RDATA Valid Before RCLK Falling (Note 30) RPOS/RNEG Valid Before RCLK Rising (Note 31) RPOS/RNEG Valid After RCLK Falling (Note 29) RDATA Valid After RCLK Falling (Note 30) RPOS/RNEG Valid After RCLK Rising (Note 31)
DS155F
fc ftclk tpwh2/tpw2 faclki tpwh1/tpw1 tr tf tsu2 th2 tsu1 tsu1 tsu1 th1 th1 th1
40 45 25 25 100 100 100 100 100 100
8.192000 2.048 50 2.048 50 194 194 194 194 194 194
60 55 85 85 -
MHz MHz % MHz % ns ns ns ns ns ns ns ns ns ns
5
CS61577
(TA = -40 to 85C; TV+, RV+ = 5%; Inputs: Logic 0 = 0V, Logic 1 = RV+)
SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup Time SCLK to CS Hold Time CS Inactive Time SCLK to SDO Valid CS to SDO High Z Input Valid To PCS Falling Setup Time PCS Rising to Input Invalid Hold Time PCS Active Low Time Notes: 33. Output load capacitance = 50pF
(Note 33)
tdc tcdh tcl tch tr, tf tcc tcch tcwh tcdv tcdz tsu4 th4 tpcsl
50 50 240 240 50 50 250 50 50 250
100 -
50 200 -
ns ns ns ns ns ns ns ns ns ns ns ns ns
tr
tf
Any Digital Output
90%
10%
90%
10%
Figure 1. Signal Rise and Fall Characteristics
tpw1 RCLK t pwl1 t su1 t pwh1 t h1 EXTENDED HARDWARE MODE OR HOST MODE (CLKE = 1)
RPOS RNEG RDATA BPV RCLK
HARDWARE MODE OR HOST MODE (CLKE = 0)
Figure 2. Recovered Clock and Data Switching Characteristics
6
DS155F
CS61577
t pw2 t pwh2 TCLK t su2 t h2
TPOS/TNEG
Figure 3. Transmit Clock and Data Switching Characteristics
t cwh CS
t cc
SCLK t dc SDI
t ch
t cl
t cch
t cdh LSB
BYTE DATA BYTE
t cdh MSB
LSB
CONTROL
Figure 4. Serial Port Write Timing Diagram
CS
t cdz
SCLK t cdv SDO CLKE = 1
Figure 5. Serial Port Read Timing Diagram
HIGH Z
PCS t su4 LEN0/1/2, TAOS, RLOOP, LLOOP, RCODE, TCODE t pcsl
VALID INPUT DATA
th4
Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram
DS155F
7
CS61577
THEORY OF OPERATION CS61577 Enhancements Relative to CS61574 Existing designs using the CS61574 can be converted to the higher performance, pin-compatible CS61577 with no changes to the PCB, external component or system software. The CS61577 provides higher performance and more features than the CS61574 including: * * * * * * * * Selection of 75 or 120 E1 output options under software or hardware control, 50 mARMS transmitter short-circuit current limiting for E1 (per OFTEL OTR-001), internally controlled pulse width for E1 output options, 35% lower power consumption, Increased transmitter immunity to signal reflections for improved signal quality, Optional AMI, B8ZS, HDB3 encoder/decoder or external line coding support, Receiver AIS (unframed all ones) detection, Improved receiver Loss of Signal handling (LOS set at power-up, reset upon receipt of 3 ones in 32 bit periods with no more than 15 consecutive zeros), Transmitter TTIP and TRING outputs are forced low when TCLK is static, The Driver Performance Monitor operates over a wider range of input signal levels. lowing individual ICs to be configured using a common set of control lines. In the Host Mode, an external processor monitors and configures the device through a serial interface. There are thirteen multi-function pins whose functionality is determined by the operating mode. (see Table 2).
Hardware Mode Control Method MODE Pin Level Line Coding AIS Detection Driver Performance Monitor Control Pins <0.2 V Extended Host Hardware Mode Mode Control Pins Serial with Parallel Interface Chip Select Floating or >(RV+)-0.2 V 2.5 V InternalAMI, B8ZS, or HDB3 Yes No External
External
No Yes
No Yes
Table 1. Differences Between Operating Modes
* *
Introduction to Operating Modes The CS61577 supports three operating modes which are selected by the level of the MODE pin as shown in Tables 1 and 2, Figure 7, and Figures A1-A3 of the Applications section. The modes are Hardware Mode, Extended Hardware Mode, and Host Mode. In Hardware and Extended Hardware Modes, discrete pins are used to configure and monitor the device. The Extended Hardware Mode provides a parallel chip select input which latches the control inputs al8
MODE EXTENDED FUNCTION PIN HARDWARE HARDWARE 3 TPOS TDATA TRANSMITTER 4 TNEG TCODE 6 RNEG BPV 7 RPOS RDATA RECEIVER/DPM 11 DPM AIS RCODE 17 MTIP 18 MRING 18 PCS 23 LEN0 LEN0 24 LEN1 LEN1 CONTROL 25 LEN2 LEN2 26 RLOOP RLOOP 27 LLOOP LLOOP 28 TAOS TAOS
HOST TPOS TNEG RNEG RPOS DPM MTIP MRING INT SDI SDO CS SCLK CLKE
Table 2. Pin Definitions
DS155F
CS61577
TAOS
LLOOP
RLOOP
LEN0/1/2
CONTROL TPOS TNEG CS62180B FRAMER CIRCUIT LINE DRIVER MRING MTIP DPM RTIP JITTER ATTENUATOR LINE RECEIVER RRING TTIP TRING
TRANSMIT TRANSFORMER
DRIVER MONITOR RPOS RNEG
RECEIVE TRANSFORMER
TCODE
RCODE
TAOS LLOOP
RLOOP
PCS
LEN0/1/2
CONTROL TTIP TDATA AMI B8ZS, HDB3, CODER RDATA LINE DRIVER TRING TRANSMIT TRANSFORMER
T1 or E1 REPEATER OR MUX
RTIP
AIS DETECT
JITTER ATTENUATOR
LINE RECEIVER
RRING
RECEIVE TRANSFORMER
BPV
AIS
P SERIAL PORT 5
CLKE
CONTROL TPOS TNEG CS62180B FRAMER CIRCUIT RPOS RNEG
CONTROL TTIP LINE DRIVER MRING MTIP DPM RTIP JITTER ATTENUATOR LINE RECEIVER RRING TRING TRANSMIT TRANSFORMER
DRIVER MONITOR
RECEIVE TRANSFORMER
Figure 7. Overview of Operating Modes
DS155F
9
CS61577
Transmitter The transmitter takes digital T1 or E1 input data and drives appropriately shaped bipolar pulses onto a transmission line through a 1:2 transformer. The transmit data (TPOS & TNEG or TDATA) is supplied synchronously and sampled on the falling edge of the input clock, TCLK. Either T1 (DSX-1 or Network Interface) or E1 CCITT G.703 pulse shapes may be selected. Pulse shaping and signal level are controlled by "line length select" inputs as shown in Table 3. For T1 DSX-1 applications, line lengths from 0 to 655 feet (as measured from the transmitter to the DSX-1 cross connect) may be selected. The five partition arrangement in Table 3 meets ANSI T1.102 and AT&T CB-119 requirements when using #22 ABAM cable. A typical output pulse is shown in Figure 8. These pulse settings can also be used to meet CCITT pulse shape requirements for 1.544 MHz operation. For T1 Network Interface applications, two additional options are provided. Note that the optimal pulse width for Part 68 (324 ns) is narrower than the optimal pulse width for DSX-1 (350 ns). The CS61577 automatically adjusts the pulse width based upon the "line length" selection made.
1.0
NORMALIZED AMPLITUDE
ANSI T1.102, AT&T CB 119 SPECIFICATIONS
0.5
0 OUTPUT PULSE SHAPE
-0.5
0 250 500 750 1000
TIME (nanoseconds)
Figure 8. Typical Pulse Shape at DSX-1 Cross Connect
The E1 G.703 pulse shape is supported with line length selections LEN2/1/0=0/0/0 or LEN2/1/0=0/0/1. As with the CS61574, LEN2/1/0=0/0/0 supports the 120 , 3 V output option without external series resistors, but will also support the 75 , 2.37 V output option with an external 4.4 resistor in series with TTIP or TRING. The new LEN2/1/0=0/0/1 code supports the 75 , 2.37 V output option without external series resistors allowing for software selection between the two E1 output options. The pulse width will meet the G.703 pulse shape template shown in Figure 9, and specified in Table 4. The CS61577 will detect a static TCLK, and will force TTIP and TRING low to prevent transmission when data is not present. When any transmit control pin (TAOS, LEN0-2 or LLOOP) is toggled, the transmitter outputs will require approximately 22 bit periods to stabilize. The transmitter will take longer to stabilize when RLOOP is selected because the timing circuitry must adjust to the new frequency.
0 1 1 1 1 0 0 0 0
1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1
0-133 FEET 133-266 FEET 266-399 FEET 399-533 FEET 533-655 FEET 75 (with 4.4 resistor) & 120 75 (without 4.4 resistor) FCC PART 68, OPT. A ANSI T1.403
DSX-1 ABAM (AT&T 600B or 600C)
E1 CCITT G.703 NETWORK INTERFACE
Table 3. Line Length Selection
10
DS155F
CS61577
Percent of nominal peak voltage 120
Receiver
269 ns
110
100 90
244 ns
194 ns
80
50
10
0
Nominal Pulse
-10
-20 219 ns 488 ns
The receiver extracts data and clock from an AMI (Alternate Mark Inversion) coded signal and outputs clock and synchronized data. The receiver is sensitive to signals over the entire range of ABAM cable lengths and requires no equalization or ALBO (Automatic Line Build Out) circuits. The signal is received on both ends of a centertapped, center-grounded transformer. The transformer is center tapped on the IC side. The clock and data recovery circuit exceeds the jitter tolerance specifications of Publications 43802, 43801, AT&T 62411, TR-TSY-000170, and CCITT REC. G.823. A block diagram of the receiver is shown in Figure 10. The two leads of the transformer (RTIP and RRING) have opposite polarity allowing the receiver to treat RTIP and RRING as unipolar signals. Comparators are used to detect pulses on RTIP and RRING. The comparator thresholds are dynamically established at a percent of the peak level (50% of peak for E1, 65% of peak for T1; with the slicing level selected by LEN2/1/0 inputs). The leading edge of an incoming data pulse triggers the clock phase selector. The phase selector chooses one of the 13 available phases which the delay line produces for each bit period. The outFor c oax ia l c able, For shielded twisted 75 loa d a nd pair, 120 load and transformer specified transformer specified in Application Section. in Application Section. 2.37 V 3V 0 0.237 V 0 0.30 V 244 ns
Figure 9. Mask of the Pulse at the 2048 kbps Interface
Transmit All Ones Select The transmitter provides for all ones insertion at the frequency of TCLK. Transmit all ones is selected when TAOS goes high, and causes continuous ones to be transmitted on the line (TTIP and TRING). In this mode, the TPOS and TNEG (or TDATA) inputs are ignored. If Remote Loopback is in effect, any TAOS request will be ignored.
Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal pulse width Ratio of the amplitudes of positive and negative 0.95 to 1.05* pulses at the center of the pulse interval Ratio of the widths of positive and negative 0.95 to 1.05* pulses at the nominal half amplitude * When configured with a 0.47 F nonpolarized capacitor in series with the TX transformer primary as shown in Figures A1, A2 and A3. Table 4. CCITT G.703 Specifications
DS155F
11
CS61577
RTIP 1:2
Data Level Slicer
RRING
Data Sampling & Clock Extraction
RPOS
Jitter Attenuator
RNEG RCLK
Edge Detector
Clock Phase Selector
Continuously Calibrated Delay Line
Figure 10. Receiver Block Diagram
put from the phase selector feeds the clock and data recovery circuits which generate the recovered clock and sample the incoming signal at appropriate intervals to recover the data. Data sampling will continue at the periods selected by the phase selector until an incoming pulse deviates enough to cause a new phase to be selected for data sampling. The phases of the delay line are selected and updated to allow as much as 0.4 UI of jitter from 10 kHz to 100 kHz, without error. The jitter tolerance of the receiver exceeds that shown in Figure 11. Additionally, this method of clock and data recovery is tolerant of long strings of consecutive zeros. The data
Minimum Performance
sampler will continuously sample data based on its last input until a new pulse arrives to update the clock phase selector. The delay line is continuously calibrated using the crystal oscillator reference clock. The delay line produces 13 phases for each cycle of the reference clock. In effect, the 13 phases are analogous to a 20 MHz clock when the reference clock is 1.544 MHz. This implementation utilizes the benefits of a 20 MHz clock for clock recovery without actually having the clock present to impede analog circuit performance. In the Hardware Mode, data at RPOS and RNEG should be sampled on the rising edge of RCLK, the recovered clock. In the Extended Hardware Mode, data at RDATA should be sampled on the falling edge of RCLK. In the Host Mode, CLKE determines the clock polarity for which output data should be sampled as shown in Table 5.
300 138 100
AT&T 62411 PEAK-TO-PEAK JITTER (unit intervals)
28 10
1 .4
.1 1
10 100 300 700 1k JITTER FREQUENCY (Hz) 10k 100k
Figure 11. Minimum Input Jitter Tolerance of Receiver (Clock Recovery Circuit and Jitter Attenuator)
12 DS155F
CS61577
MODE (pin 5) LOW (<0.2V) HIGH (>(V+) - 0.2V) HIGH (>(V+) - 0.2V) MIDDLE (2.5V) CLKE (pin 28) X Clock Edge for Valid Data Rising Rising Rising Rising Falling Falling Falling Rising Falling
DATA RPOS RNEG RPOS RNEG SDO RPOS RNEG SDO RDATA
CLOCK RCLK RCLK RCLK RCLK SCLK RCLK RCLK SCLK RCLK
LOW
This means that RCLK will smoothly transition to the new frequency. If ACLKI is not present, then the crystal oscillator of the jitter attenuator is forced to its center frequency. Table 6 shows the status of RCLK upon LOS.
HIGH
X
X = Don't Care
Crystal present? No Yes Yes
ACLKI present? Yes No Yes
Source of RCLK ACLKI Centered Crystal ACLKI via the Jitter Attenuator
Table 5. Data Output/Clock Relationship
Loss of Signal The receiver will indicate loss of signal after power-up, reset or upon receiving 175 consecutive zeros. A digital counter counts received zeros, based on RCLK cycles. A zero is received when the RTIP and RRING inputs are below the input comparator slicing threshold level established by the peak detector. After the signal is removed for a period of time the data slicing threshold level decays to approximately 300 mVpeak. The receiver reports loss of signal by setting the Loss of Signal pin, LOS, high. If the serial interface is used, the LOS bit will be set and an interrupt will be issued on INT (unless disabled). LOS will return low (asserting the INT pin again in Host Mode) upon receipt of 3 ones in 32 bit periods with no more than 15 consecutive zeros. Note that in the Host Mode, LOS is simultaneously available from both the register and pin 12. RPOS/RNEG or RDATA are forced low during LOS unless the jitter attenuator is disabled. (See "Jitter Attenuator" section) If ACLKI is present during the LOS state, ACLKI is switched into the input of the jitter attenuator, resulting in RCLK matching the frequency of ACLKI. The jitter attenuator buffers any instantaneous changes in phase between the last recovered clock and the ACLKI reference clock.
DS155F
Table 6. RCLK Status at LOS
Jitter Attenuator The jitter attenuator reduces wander and jitter in the recovered clock signal. It consists of a 32-bit FIFO, a crystal oscillator, a set of load capacitors for the crystal, and control logic. The jitter attenuator exceeds the jitter attenuation requirements of Publications 43802 and REC. G.742. The jitter attenuator works in the following manner. The recovered clock and data are input to the FIFO with the recovered clock controlling the FIFO's write pointer. The crystal oscillator controls the FIFO's read pointer which reads data out of the FIFO and presents it at RPOS and RNEG (or RDATA). The update rate of the read pointer is analogous to RCLK. By changing the load capacitance that the IC presents to the crystal, the oscillation frequency is adjusted to the average frequency of the recovered signal. Logic determines the phase relationship between the read and write pointers and decides how to adjust the load capacitance of the crystal. Thus the jitter attenuator behaves as a first-order phase lock loop. Jitter is absorbed in the FIFO according to the jitter transfer characteristic shown in Figure 12.
13
CS61577
0 a) Minimum Attenuation Limit 10 20 30 40 50 60 1 10 Measured Performance b) Maximum Attenuation Limit 62411 Requirements
Local Loopback Local loopback is selected by taking LLOOP, pin 27, high or by setting the LLOOP register bit via the serial interface. The local loopback mode takes clock and data presented on TCLK, TPOS, and TNEG (or TDATA), sends it through the jitter attenuator and outputs it at RCLK, RPOS and RNEG (or RDATA). If the jitter attenuator is disabled, it is bypassed. Inputs to the transmitter are still transmitted on TTIP and TRING, unless TAOS has been selected in which case, AMI-coded continuous ones are transmitted at the TCLK frequency. The receiver RTIP and RRING inputs are ignored when local loopback is in effect. Remote Loopback Remote loopback is selected by taking RLOOP, pin 26, high or by setting the RLOOP register bit via the serial interface. In remote loopback, the recovered clock and data input on RTIP and RRING are sent through the jitter attenuator and back out on the line via TTIP and TRING. Selecting remote loopback overrides any TAOS request (see Table 6). The recovered incoming signals are also sent to RCLK, RPOS and RNEG (or RDATA). A remote loopback occurs in response to RLOOP going high.
RLOOP TAOS Input Input Signal Signal 0 0 1 0 1 X Source of Data for TTIP & TRING TDATA all 1s RTIP & RRING Source of Clock for TTIP & TRING TCLK TCLK RTIP & RRING (RCLK)
Attenuation in dB
100 1k Frequency in Hz
10 k
Figure 12. Typical Jitter Transfer Function
The FIFO in the jitter attenuator is designed to prevent overflow and underflow. If the jitter amplitude becomes very large, the read and write pointers may get very close together. Should they attempt to cross, the oscillator's divide by four circuit adjusts by performing a divide by 3 1/2 or divide by 4 1/2 to prevent the overflow or underflow. During this activity, data will never be lost. The 32-bit FIFO in the CS61577 attenuator allows it to absorb jitter with minimum data delay in T1 and E1 switching or transmission applications. Like the CS61574, the CS61577 will tolerate large amplitude jitter (>23 UIpp) by tracking rather than attenuating it, preventing data errors so that the jitter may be absorbed in external frame buffers. The jitter attenuator may be bypassed by pulling XTALIN to RV+ through a 1 k resistor and providing a 1.544 MHz (or 2.048 MHz) clock on ACLKI. RCLK may exhibit quantization jitter of approximately 1/13 UIpp and a duty cycle of approximately 30% (70%) when the attenuator is disabled.
Notes: 1. X = Don't Care. The identified All Ones Select input is ignored when the indicated loopback is in effect. 2. Logic 1 indicates that Loopback or All Ones option is selected.
Table 7. Interaction of RLOOP with TAOS
14 DS155F
CS61577
Simultaneous selection of local and remote loopback modes is not valid (see Reset). In the Extended Hardware Mode the transmitted data is looped before the AMI/B8ZS/HDB3 encoder/decoder during remote loopback so that the transmitted signal matches the received signal, even in the presence of received bipolar violations. Data output on RDATA is decoded, however, if RCODE is low. Alarm Indication Signal In the Extended Hardware Mode, the receiver sets the output pin AIS high when less than 3 zeros are detected out of 2048 bit periods. Line Code Encoder/Decoder In the Extended Hardware Mode, three line codes are available: AMI, B8ZS and HDB3. The input to the encoder is TDATA. The outputs from the decoder are RDATA and BPV (Bipolar Violation Strobe). The encoder and decoder are selected using the LEN2, LEN1, LEN0, TCODE and RCODE pins as shown in Table 8.
LEN 2/1/0 000 010-111 HDB3 B8ZS Encoder Encoder AMI Encoder HDB3 Decoder B8ZS Decoder
Parallel Chip Select In the Extended Hardware Mode, PCS can be used to gate the digital control inputs: TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS. Inputs are accepted on these pins only when PCS is low and will immediately change the operating state of the device. Therefore, when cycling PCS to update the operating state, the digital control inputs should be stable for the entire PCS low period. The digital control inputs are ignored when PCS is high Driver Performance Monitor To aid in early detection and easy isolation of non-functioning links, the IC is able to monitor transmit drive performance and report when the driver is no longer operational. This feature can be used to monitor either the device's performance or the performance of a neighboring driver. The driver performance monitor indicator is normally low, and goes high upon detecting a driver failure. The driver performance monitor consists of an activity detector that monitors the transmitted signal when MTIP is connected to TTIP and MRING is connected to TRING. DPM will go high if the absolute difference between MTIP and MRING does not transition above or below a threshold level within a time-out period. In the Host Mode, DPM is available from the register and pin 11. Whenever more than one line interface IC resides on the same circuit board, the effectiveness of the driver performance monitor can be maximized by having each IC monitor performance of a neighboring IC, rather than having it monitor its own performance. Note that a CS61577 can not be used to monitor a CS61574 due to output stage differences.
TCODE (Transmit Encoder Selection) RCODE (Receiver Decoder Selection)
LOW HIGH LOW HIGH
AMI Decoder
Table 8. Encoder/Decoder Selection
DS155F
15
CS61577
CS SCLK SDI SDO
R/W
0
0
0
0
1
0
0
D0 D0
D1 D1
Address/Command Byte
D2 D3 D4 D5 Data Input/Output D2 D3 D4 D5
D6 D6
D7 D7
Figure 13. Input/Output Timing
Serial Interface In the Host Mode, pins 23 through 28 serve as a microprocessor/microcontroller interface. One on-board register can be written to via the SDI pin or read from via the SDO pin at the clock rate determined by SCLK. Through this register, a host controller can be used to control operational characteristics and monitor device status. The serial port read/write timing is independent of the system transmit and receive timing. Data transfers are initiated by taking the chip select input, CS, low (CS must initially be high). Address and input data bits are clocked in on the rising edge of SCLK. The clock edge on which output data is stable and valid is determined by CLKE as shown in Table 5. Data transfers are terminated by setting CS high. CS may go high no sooner than 50 ns after the rising edge of the SCLK cycle corresponding to the last write bit. For a serial data read, CS may go high any time to terminate the output. Figure 13 shows the timing relationships for data transfers when CLKE = 1. When CLKE = 1, data bit D7 is held until the falling edge of the 16th clock cycle. When CLKE = 0, data bit D7 is held until the rising edge of the 17th clock cycle. SDO goes High-Z after CS goes high or at the end of the hold period of data bit D7.
LSB, first bit
0 1 2 3 4 5 6
R/W ADD0 ADD1 ADD2 ADD3 ADD4 -
Read/Write Select; 0 = write, 1 = read LSB of address, Must be 0 Must be 0 Must be 0 Must be 0 Must be 1 Reserved - Must be 0
Table 9. Address/Command Byte
An address/command byte, shown in Table 9, precedes a data register. The first bit of the address/command byte determines whether a read or a write is requested. The next six bits contain the address. The line interface responds to address 16 (0010000). The last bit is ignored. The data register, shown in Table 10, can be written to the serial port. Data is input on the eight clock cycles immediately following the address/command byte. Bits 0 and 1 are used to clear an interrupt issued from the INT pin, which occurs in response to a loss of signal or a problem with the output driver.
LSB: first bit in
0 1 2 3 4 5 6 MSB: last bit in 7
clr LOS clr DPM LEN0 LEN1 LEN2 RLOOP LLOOP TAOS
Clear Loss of Signal Clear Driver Performance Monitor Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Lenght Select Remote Loopback Local Loopback Transmit All Ones Select
NOTE: Setting 5, 6, & 7 to 101 or 111 puts the CS61577 into a factory test mode.
Table 10. Input Data Register
16
DS155F
CS61577
Writing a "1" to either "Clear LOS" or "Clear DPM" over the serial interface has three effects: 1) The current interrupt on the serial interface will be cleared. (Note that simply reading the register bits will not clear the interrupt). 2) Output data bits 5, 6 and 7 will be reset as appropriate. 3) Future interrupts for the corresponding LOS or DPM will be prevented from occurring. Writing a "0" to either "Clear LOS" or "Clear DPM" enables the corresponding interrupt for LOS or DPM. Input bits 5/6/7=111 and 5/6/7=101 are the same request, and cause the line interface to enter into the factory test mode. In other words, when RLOOP=1 (Bit 5) and TAOS=1 (Bit 7), LOOP (Bit 6) is a don't care. For normal operation, RLOOP and TAOS should not be simultaneously selected via the serial interface. Output data from the serial interface is presented as shown in Tables 11 and 12. Bits 2, 3 and 4 can be read to verify line length selection. Bits 5, 6 and 7 must be decoded. Codes 101, 110 and 111 (Bits 5, 6 and 7) indicate intermittent losses of signal and/or driver problems. SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in applications where the host processor has a bi-directional I/O port.
Bits 6 0 0 1 1 0 0
5 0 0 0 0 1 1
Reset has occurred or no program input. TAOS in effect. LLOOP in effect. TAOS/LLOOP in effect. RLOOP in effect DPM changed state since last "clear DPM" occured. 1 1 0 LOS changed state since last "clear LOS" occured. 1 1 1 LOS and DPM have changed state since last "clear LOS" and "clear DPM". Table 12. Coding for Serial Output bits 5,6,7
7 0 1 0 1 0 1
Status
Power On Reset / Reset Upon power-up, the IC is held in a static state until the supply crosses a threshold of approximately 3 Volts. When this threshold is crossed, the device will delay for about 10 ms to allow the power supply to reach operating voltage. After this delay, calibration of the delay lines used in the transmit and receive sections commences. The delay lines can be calibrated only if a reference clock is present. The reference clock for the receiver is provided by the crystal oscillator, or ACLKI if the oscillator is disabled. The reference clock for the transmitter is provided by TCLK. The initial calibration should take less than 20 ms. In operation, the delay lines are continuously calibrated, making the performance of the device independent of power supply or temperature variations. The continuous calibration function forgoes any requirement to reset the line interface when in operation. However, a reset function is available which will clear all registers. In the Hardware and Extended Hardware Modes, a reset request is made by simultaneously setting both the RLOOP and LLOOP pins high for at least 200 ns. Reset will initiate on the falling edge of the reset request (falling edge of RLOOP and LLOOP). In the Host Mode, a reset is initiated by simultaneously writing RLOOP and LLOOP to
17
LSB: first bit in
0 1 2 3 4
LOS DPM LEN0 LEN1 LEN2
Loss of Signal Driver Performance Monitor Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Lenght Select
Table 11. Output Data Bits 0 - 4
DS155F
CS61577
the register. In either mode, a reset will set all registers to 0 and force the oscillator to its center frequency before initiating calibration. A reset will also set LOS high. Power Supply The device operates from a single +5 Volt supply. Separate pins for transmit and receive supplies provide internal isolation. These pins should be connected externally near the device and decoupled to their respective grounds. TV+ must not exceed RV+ by more than 0.3V. Decoupling and filtering of the power supplies is crucial for the proper operation of the analog circuits in both the transmit and receive paths. A 1.0 F capacitor should be connected between TV+ and TGND, and a 0.1 F capacitor should be connected between RV+ and RGND. Use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. A 68 F tantalum capacitor should be added close to the RV+/RGND supply. Wire-wrap breadboarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors.
Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering.
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CS61577
PI N DE SCR I PT I ONS ( [WHQGHG +DUGZDUH 0RGH
5
4
3
2
1
28 27 26 25
6
7 top view
24
23 22
8
9 10
21
20
11
12 13 14 15 16 17 18
19
+RVW 0RGH
5
4
3
2
1
28 27 26 25
6
7 top view
24
23 22
8
9 10
21
20
11
12 13 14 15 16 17 18
19
DS155F
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CS61577
Power Supplies RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 Volts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 Volts. TGND - Ground, Transmit Driver, Pin 14. Power supply ground for the transmit driver; typically 0 Volts. TV+ - Power Supply, Transmit Driver, Pin 15. Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than 0.3 V. Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or 2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying XTALIN, Pin 9 to RV+ through a 1 k resistor, and floating XTALOUT, Pin 10. Overdriving the oscillator with an external clock is not supported. 6HH $SSHQGL[ $ Control ACLKI - Alternate External Clock Input, Pin 1. A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground. During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator. CLKE - Clock Edge, Pin 28. (Host Mode) Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of SCLK. CS - Chip Select, Pin 26. (Host Mode) This pin must transition from high to low to read or write the serial port. INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor.
20
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CS61577
LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line length selection. Also controls the receiver slicing level and the line code in Extended Hardware Mode. LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes) Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request. Inputs on RTIP and RRING are ignored. MODE - Mode Select, Pin 5. Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial control port is used to control the line interface and determine its status. Grounding the MODE pin puts the line interface in the Hardware Mode, where configuration and status are controlled by discrete pins. Floating the MODE pin or driving it to +2.5 Vselects the Extended Hardware Mode, where configuration and status are controlled by discrete pins. When floating MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2). PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode) Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS inputs. RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode) Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting RCODE high enables the AMI receiver decoder (see Table 8). RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes) Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator (if active) and through the driver back to the line. The recovered signal is also sent to RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored. In the Host Mode, simultaneous selection of RLOOP & TAOS enables a factory test mode. Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset. SCLK - Serial Clock, Pin 27. (Host Mode) Clock used to read or write the serial port registers. SCLK can be either high or low when the line interface is selected using the CS pin. SDI - Serial Data Input, Pin 24. (Host Mode) Data for the on-chip register. Sampled on the rising edge of SCLK. SDO - Serial Data Output, Pin 25. (Host Mode) Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output.
DS155F
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CS61577
TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by TCLK. In the Host Mode, simultaneous selection of RLOOP & TAOS enables a factory test mode. TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode) Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting TCODE high enables the AMI transmitter encoder . Data RDATA - Receive Data - Pin 7. (Extended Hardware Mode) Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK. RCLK - Recovered Clock, Pin 8. The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator.. RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host Modes) The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive pulse received on the RRING pin generates a logic 1 on RNEG. RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20. The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data and clock are recovered and output on RCLK and RPOS/RNEG or RDTA. TCLK - Transmit Clock, Pin 2. The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are sampled on the falling edge of TCLK. TDATA - Transmit Data, Pin 3. (Extended Hardware Mode) Transmitter NRZ input data which passes through the line code encoder, and is then driven on to the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK. TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and Host Modes) Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted.
22
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CS61577
TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. The transmitter output is designed to drive a 25 load between TTIP and TRING. A transformer is required as shown in Table A1. Status AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode) AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode) BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been enabled. DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes) DPM goes high if no activity is detected on MTIP and MRING. LOS - Loss of Signal, Pin 12. LOS goes high when 175 consecutive zeros have been received. LOS returns low when 3 ones are received within 32 bit periods with no more than 15 consecutive zeros. When in the loss of signal state RPOS/RNEG or RDATA are forced low, and ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator. MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) These pins are normally connected to TTIP and TRING and monitor the output of a line interface IC. If the INT pin in the host mode is used, and the monitor is not used, writing "clear DPM" to the serial interface will prevent an interrupt from the driver performance monitor.
DS155F
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CS61577
E1 E
4.20
4.45
4.57 0.165 0.175 0.180
2.29 0.33
2.79 0.41
3.04 0.090 0.110 0.120 0.53 0.013 0.016 0.021
12.32 12.45 12.57 0.485 0.490 0.495
D1 D
11.43 11.51 11.58 0.450 0.453 0.456 9.91 10.41 10.92 0.390 0.410 0.430
1.19 1.27 1.35 0.047 0.050 0.053
B
e A1 D2/E2 A
24
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CS61577
APPLICATIONS
+5V + 68 F RGND 28 Control & Monitor 1 12 11 RV+ 5 7 6 Frame Format Encoder/ Decoder 8 3 4 2 9 XTL 10 CLKE ACLKI
LOS
0.1 F 21 RV+ 15 TV+
+
1.0 F TGND
+5V 100 k
SCLK CS
INT
27 26 23 24 25 P Serial Port
DPM
SDI SDO
MODE RPOS RNEG RCLK
TPOS
RTIP
19 R1 20 17 18 16 13 R2
1 2 3 5 2CT:1 PE-65351 0.47 F 2 6 RECEIVE 6 LINE
RRING
MTIP
TNEG TCLK
XTALIN XTALOUT RGND 22
MRING TRING
TGND 14 TTIP
1 TRANSMIT 5 LINE
1:2CT PE-65351
Figure A1. T1 Host Mode Configuration Frequency MHz 1.544 (T1) 2.048 (E1) Crystal XTL 6.176 MHz 8.192 MHz Cable 100 120 75 LEN2/1/0 0/1/1 - 1/1/1 0/0/0 0/0/0 0/0/1 R3 not used not used R1 and R2 200 240 150
4.4 not used
Table A1. External Component Values
Line Interface Figures A1-A3 show typical T1 and E1 line interface application circuits. Table A1 shows the external components which are specific to each application. Figure A1 illustrates a T1 interface in the Host Mode. Figure A2 illustrates a 120 E1 interface in the Hardware Mode. Figure A3 illustrates a 75 E1 interface in the Extended Hardware Mode.
The 1:2 receiver transformer has a grounded center tap on the IC side. Resistors R1 and R2 between the RTIP and RRING pins to ground provide the termination for the receive line. The transmitter also uses a 1:2 transformer. A 0.47 F capacitor is required in series with the transmit transformer primary. This capacitor is needed to prevent any output stage imbalance from resulting in a DC current through the transformer primary. This current might saturate the transformer producing an output offset level shift.
25
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CS61577
+5V + 68 F RGND 28 1 Control & Monitor 26 27 12 11 5 7 6 Frame Format Encoder/ Decoder 8 3 4 2 9 XTL 10 TAOS ACLKI RLOOP LLOOP LOS DPM MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND 22 TGND 14
MTIP
0.1 F 21 RV+ 15 TV+
+
1.0 F TGND
LEN0 LEN1 LEN2
23 24 25
Line Length Setting
RTIP
19 R1 20 R2
1 2 3 5 2CT:1 PE-65351 0.47 F 2 6 RECEIVE 6 LINE
RRING
17 18 16 13
MRING TRING TTIP
1 TRANSMIT 5 LINE
1:2CT PE-65351
Figure A2. 120 , E1 Hardware Mode Configuration
+5V + 68 F RGND 17 18 6 28 Control & Monitor 1 26 27 12 11 5 4 7 Frame Format Encoder/ Decoder 8 3 2 9 XTL 10 RCODE PCS BPV TAOS ACLKI RLOOP LLOOP LOS AIS MODE TCODE RDATA RCLK TDATA TCLK XTALIN XTALOUT RGND 22 TGND 14 TRING TTIP 16 13 R3 RRING 20 R2 RTIP 19 R1 1 2 3 5 2CT:1 PE-65351 0.47 F 2 6 RECEIVE 6 LINE LEN0 LEN1 LEN2 23 24 25 Line Length Setting 0.1 F 21 RV+ 15 TV+ + 1.0 F TGND
1 TRANSMIT 5 LINE
1:2CT PE-65351
R3 is used for LEN2/1/0 = 0/0/0, but not required with LEN2/1/0 = 0/0/1.
Figure A3. 75 , E1 Extended Hardware Mode Configuration
26 DS155F
CS61577
Transformers Recommended transmitter and receiver transformer specifications are shown in Table A2. The transformers in Table A3 have been tested and recommended for use with the CS61577. Refer to the "Telecom Transformer Selection Guide" for detailed schematics which show how to connect the line interface IC with a particular transformer. Selecting an Oscillator Crystal Specific crystal parameters are required for proper operation of the jitter attenuator. It is recommended that D 0+] FU\VWDO EH XVHG IRU 7 DSSOLFDWLRQV DQG DQ 0+] FU\VWDO EH XVHG IRU ( DSSOLFDWLRQV. 6HH $SSHQGL[ $ Transmit Side Jitter Attenuation Turns Ratio Primary Inductance Primary Leakage Inductance Secondary Leakage Inductance Interwinding Capacitance ET-constant 1:2 CT 5% 600 H min. @ 772 kHz 1.3 H max. @ 772 kHz 0.4 H max. @ 772 kHz Line Protection 23 pF max. 16 V-s min. for T1 12 V-s min. for E1 Secondary protection components can be added to provide lightning surge and AC power-cross immunity. Refer to the "Telecom Line Protection Application Note" for detailed information on the different electrical safety standards and specific application circuit recommendations. In some applications it is desirable to attenuate jitter from the signal to be transmitted. A CS61577 in local loopback mode can be used as a jitter attenuator. The inputs to the jitter attenuator are TPOS, TNEG, TCLK. The outputs from the jitter attenuator are RPOS, RNEG and RCLK.
Table A2. Transformer Specifications
Turns Ratio(s) 1:2CT
Manufacturer Pulse Engineering Schott Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering
Part Number PE-65351 67129300 0553-0013-HC PE-64951 0553-0013-1J PE-65761 S553-0013-03 PE-65835
Package Type 1.5 kV through-hole, single
dual 1:2CT dual 1:2CT 1:2CT
1.5 kV through-hole, dual 1.5 kVsurface-mount, dual 3 kV through-hole, single EN60950, EN41003 approved
Table A3. Recommended Transformers
DS155F
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CS61577
APPENDIX A. RECOMMENDED CRYSTAL SPECIFICATIONS
Cirrus Logic telecommunication devices that offer jitter attenuation require crystals with specifications for frequency pullability. The crystal oscillation freque ncy is dictated by capaci tive loading, which is controlled by the chip. Therefore, the crystals must meet the following specifications.
6.176 MHz Crystal Performance Specifications
Parameter Total Frequency Range Operating Frequency Cload = 11.6 pF Cload = 19.0 pF Cload = 37.0 pF (Note 1) (Note 2) (Note 3) (Note 2) Min 6.176803 6.175846 Typ 370 6.176000 Max 390 6.176154 6.175197 Units ppm MHz MHz MHz
8.192 MHz Crystal Performance Specifications
Parameter Total Frequency Range Operating Frequency Cload = 11.6 pF Cload = 19.0 pF Cload = 37.0 pF (Note 1) (Note 2) (Note 3) (Note 2) Min 8.192410 8.191795 Typ 210 8.192000 Max 245 8.192205 8.191590 Units ppm MHz MHz MHz
Notes:
1. With Cload varying from 11.6 to 37.0 pF at a given temperature. 2. Measured at -40 to 85C. 3. Measured with Saunders 150D meter at 25 C.
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REVISION HISTORY
Revision
F
Date
Jul '09
Changes
Removed development system info. (No longer supported). Removed PDIP option. Changed PLCC package option to lead-free.
DS155F2
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CS61577
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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